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a
FEATURES On-Chip Regulator PLL Demodulator On-Chip VCO No Trims Excellent Sensitivity 28-Lead SSOP Package APPLICATIONS DECT/PWT/WLAN TDMA FM/FSK Systems
IFIN
IF Transceiver Subsystem AD6402
FUNCTIONAL BLOCK DIAGRAM
RSSI LIMITER/FILTER PLL DEMOD TXOUT TXOUTB 2 CFILT DOUT DFILP
AD6402
VCO IF VCO DC OFFSET COMP MODE CONTROL
1
PLLOUT
REFSEL COFF REFIN
VOLTAGE REGULATOR
FMMOD2 VREF FMMOD1
GENERAL DESCRIPTION
The AD6402 is a complete transceiver subsystem for use in high bit rate radio systems employing FM or FSK modulation. It is optimized for use in time domain multiple access (TDMA) systems with communications rates of approximately 1 MBPS. The AD6402 integrates key functions, including VCOs and a low drop-out voltage regulator. The AD6402 operates directly from an unregulated battery supply of 3.1 V to 4.5 V and provides a regulated voltage output which can be used for VCO supply regulation on a companion RF chip such as the AD6401. The AD6402 transceiver consists of a mixer, integrated IF bandpass filter, IF limiter with RSSI detection, VCO, PLL demodulator and a low dropout voltage regulator. On receive, it downconverts an IF signal in the 110 MHz range to a second IF frequency, this frequency being determined by the demodulator reference divide ratios. It then filters, amplifies, and demodulates this signal. The AD6402 provides a filtered baseband
VREG VBATT SLREF
CTL1...3
MODOUT
data output. On transmit, it accepts a Gaussian Frequency Shift Keying (GFSK) baseband signal, low-pass filters the signal if required using the on-chip op amp and modulates the IF VCO by varying the bias voltage on an off-chip varactor diode used in the tank circuit. The AD6402 has multiple power-down modes to maximize battery life. It operates over a temperature range of -25C to +85C and is packaged in a JEDEC standard 28-lead smallshrink outline (SSOP) surface-mount package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD6402-SPECIFICATIONS
AD6402ARS
Parameter IF BANDPASS FILTER Center Frequency Rejection Conditions REFIN = 13.824 MHz, REFSEL <0.2 V CC FO 3.0 MHz FO 4.7 MHz FO 6.0 MHz Min Typ 20.736 7 13 16 30 -80 Max Units MHz dBc dBc dBc dBc dBm
Stop Band Rejection RECEIVER Sensitivity RSSI Low High Slope Output Impedance DEMODULATOR Gain Offset Lock Time DATA FILTER OP AMP Gain Slew Rate Gain Bandwidth Output Swing Low Output Swing High Output Impedance IF VCO Frequency SSB Phase Noise Output Power 2nd Harmonic 3rd Harmonic TRANSMIT FILTER OP AMP Open Loop Gain Unity Gain Bandwidth Output Slew Rate Minimum Input Voltage Maximum Input Voltage Minimum Output Voltage Maximum Output Voltage POWER CONTROL Logical High Threshold Logical Low Threshold Turn-On Response Time
FM Modulated 576 kHz, FM Deviation 288 kHz BT = 0.5, Demod Output SNR = 10 dB, RS = 150 VOUT = 0.2 V, R S = 150 VOUT = 1.8 V, R S = 150 See Figure 4
-85 -5 20 4 1.2 -200 200 20 2 8 15 0.2 VCC-0.2 50 131 -139 -12 -22 -24 75 12 5 1 VCC-0.2 0.2 VCC-0.2 0.8 x VCC 0.2 x VCC 0.5 1.3 1.5 2.95 200 1 200 30 17 26 6 1.55 +200
dBm dBm mV/dB k V/MHz mV s s
At Data Filter Output Referred to SLREF From SLEEP Mode From RXLOCK Mode
CLOAD = 30 pF CLOAD = 30 pF
V/s MHz V V MHz dBc/Hz dBm dB dB dB MHz V/s V V V V V V s V V s s s mA mA mA mA
Note 1 @ 5 MHz Offset Differential RLOAD = 300
CLOAD = 30 pF CLOAD = 30 pF
VCC Steady State
VOLTAGE REFERENCE
SLREF SUPPLY REGULATOR Output Voltage Turn-On Time Line Regulation Load Regulation POWER SUPPLY Supply Current
For Battery Voltages from 3.1 V to 4.5 V 1 mV Settling, C LOAD = 100 nF 200 mV Battery Step; 5 mV Settling 10 A to 30 mA Step; 5 mV Settling All VCC at 2.85 V RXLOCKP RXLOCK RXDEMOD TRANSMIT STANDBY
2.75
SLEEP
NOTES 1 Using test tank circuit as shown. Specifications subject to change without notice.
300 10
A A
-2-
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AD6402
RECOMMENDED OPERATING CONDITIONS
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 V-4.5 V IFVCC1, IFVCC2, PLLVCC . . . . . . . . . . . . . . . . . . . .2.85 V Operating Temperature Range . . . . . . . . . . . -25C to +85C
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
TXOUTB 1 MODOUT 2 FMMOD2 3 FMMOD1 4 VCOGND 5 VCO 6
28 TXOUT 27 REFSEL 26 IFVCC1 25 IFIN
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering (60 sec) . . . . . . . . . . . . +300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. Thermal Characteristics: 28-lead SSOP package: JA = 109C/W.
AD6402
24 IFGND
TOP VIEW 23 RSSI VREG 7 (Not to Scale) 22 IFVCC2 VBAT 8 CTL3 9 CTL2 10 CTL1 11 CFILT 12 COFF 13 21 PLLGND 20 PLLVCC 19 SLREF 18 DOUT 17 DFILP 16 PLLOUT 15 REFIN
ORDERING GUIDE
REXT 14
Model AD6402ARS AD6402ARS-REEL
Temperature Range -25C to +85C -25C to +85C
Package Description 28-Lead SSOP 28-Lead SSOP
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Mnemonic TXOUTB MODOUT FMMOD2 FMMOD1 VCOGND VCO VREG VBAT CTL3 CTL2 CTL1 CFILT COFF REXT REFIN PLLOUT DFILP DOUT SLREF PLLVCC PLLGND IFVCC2 RSSI IFGND IFIN IFVCC1 REFSEL TXOUT
Function Transmit IF VCO Buffer Inverting Output Frequency Modulator Filter Op Amp Output Frequency Modulator Filter Op Amp Noninverting input Frequency Modulator Filter Op Amp Inverting input IF VCO Ground IF VCO Tank Connection Regulated Supply Output for RF VCO (Supplies Internal IF VCO, Mode Control, Bandgap Reference, and COFF Buffer) Battery Supply Voltage Input to Internal Regulator and COFF Charge Pump Mode Control Input 3, CMOS Logical Level Mode Control Input 2, CMOS Logical Level Mode Control Input 1, CMOS Logical Level PLL Demodulator Loop Filter Capacitor PLL Demodulator Frequency Offset Voltage Track/Hold Capacitor External Current-Setting Resistor Baseband Reference Frequency Input, 100 mV p-p, AC Coupled PLL Demodulator Output Data Filter Voltage-Follower Input Data Filter Voltage-Follower Output PLL Demodulator Output DC Reference Voltage PLL Demodulator and Data Filter Supply Input PLL Demodulator and Data Filter Ground IF Limiter Supply Input 1 RSSI Output IF Stage, Mixer, Band Pass Filter, IF VCO Buffer, Tx Op Amp, Mode Control, and Regulator Ground IF Mixer Input, ZO = 150 Z IF Mixer, Limiter 1, IF Filter, IF VCO Buffer Reference Frequency Select; IF = 1.5x or 2.5x Reference Frequency, CMOS Logical Level Input Transmit IF VCO Buffer Output
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6402 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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-3-
AD6402
VCO 1.2k VTUNE 1nF 4.7nF 47pF 8pF 39nH VCOGND
AD6402
330 100pF 180pF MODOUT 330 TXMOD
SMV 1204-37
SMV 1204-36 TXIF+ 240 TXIF-
1nF
TXOUT
FMMOD2 FMMOD1
1nF TXOUTB 330
150pF VCCI
Figure 1.
OVERVIEW
The AD6402 forms the basis of a highly integrated RF transceiver with the benefits of increased sensitivity and wide dynamic range that a dual-conversion architecture provides. The IC contains a low dropout voltage regulator to isolate the IF and demodulator VCOs from variation in the battery voltage, such as power-supply transients caused by the PA. The AD6402 also provides control circuitry that allows subcircuits to be turned off and on as necessary to minimize power consumption.
Operation During Receive
equal to the sum of the IF frequency plus the frequency of the PLL demodulator input as defined by the reference clock divider ratios. The transmit IF VCO uses an external tank circuit. This signal is upconverted to the transmit frequency in the RF mixer section of the radio. Using a transmit IF VCO prevents two problems: feedback from the PA at the RF frequency does not cause distortion in the modulating circuit because the frequencies are widely separated and the IF tank circuit can be optimized for modulation linearity. The output of the transmit VCO passes through buffer amplifier and leaves the AD6402 via an optional LC filter between the RF and IF ICs. The output of the LC filter may then be fed to a transmit upconversion mixer for conversion to the final RF frequency.
Onboard Voltage Regulation
The AD6402 contains the second mixer, integrated second-IF bandpass filter, logarithmic-limiting amplifier, and PLL demodulator. A SAW IF bandpass filter is usually required at the IF input in order to provide channel selectivity. The placement of the SAW filter in the signal path between the AD6402 and the RF section and the partitioning of the receiver's RF and IF receive circuits minimizes the leakage around the SAW filter and maximizes the RF to IF isolation. The output of the SAW filter enters the AD6402 via the second downconversion mixer. This mixer is a high gain, doublybalanced Gilbert-cell type. The mixer downconverts the signal to the second IF, which is 1.5 x or 2.5 x the reference frequency. This multiple is determined by the state of the REFSEL pin. An on-chip two section bandpass filter provides additional selectivity to provide attenuation of adjacent channels. The VCO control voltage output of the PLL demodulator tunes this filter to the second IF. The bandpass filter's output enters a successive-detection logarithmic-limiting IF amplifier. The RSSI detectors are distributed across the entire IF strip, including the mixer, and provide 80 dB RSSI range. The IF strip's limiting gain also exceeds 80 dB. The RSSI signal is low-pass filtered and proceeds off-chip to the baseband subsystem. The limited output of the logarithmic amplifier enters a PLL demodulator, which provides demodulation of the received signal. The PLL uses an integrated VCO with no external components.
Operation During Transmit
The AD6402 contains a low dropout voltage regulator to specifically isolate the VCOs and synthesizer from the voltage "kick" that occurs when a power amplifier switches on and the battery voltage abruptly drops. The AD6402 uses an integral vertical PNP pass transistor. The regulator in the AD6402 IF IC supplies the voltage for the VCOs on both the RF section and AD6402. The other sections of the AD6402 should be powered from an independently regulated source at 2.85 V. Since the VCOs are isolated from this source, possible problems due to VCO supply pushing are considerably reduced.
Frequency Control
The AD6402 requires an external synthesizer to provide the control voltages for the tank circuit of the IF VCO. Normally this will be the IF section of a dual synthesizer controlling both IF and RF frequency generation. It is recommended that the VCO on the RF section implement the channel selection on transmit and receive; the VCO on the AD6402 may therefore operate at a fixed frequency. This accomplishes two goals: first, the IF VCO being modulated can be optimized for modulation linearity and the RF VCO can be optimized for tuning range, and second, feedback from the PA at will not couple into the modulating circuit to cause spurious responses. All key sections of the AD6402 may be powered up or down as necessary to minimize power consumption and maximize battery life.
The transmit signal path consists of a low-pass filter that can be user configured for antialiasing of a baseband transmit signal. An IF VCO, which should be tuned to a frequency equal to the receive IF frequency plus the desired demodulator input frequency, may be open-loop modulated by the transmit signal for FM and FSK schemes. The receive IF mixer uses high side mixing and therefore the IF VCO should be set to a frequency
-4-
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AD6402
Table I. Power Management Functionality
TL1 0 0 0 1 1 1
CTL2 0 0 1 X 0 1
CTL3 0 1 0 0 1 1
PLL BIAS - - ON ON OFF ON
PLL LOCK - - ON OFF OFF ON
PLL DMOD - - OFF ON OFF OFF
REF OFF OFF ON ON ON ON
REG OFF ON ON ON ON ON
RX - - OFF ON OFF ON
VCO - - ON ON ON ON
MODE SLEEP STANDBY RXLOCK RXDMOD TRANSMIT RXLOCKP
The AD6402 has six operating modes: SLEEP, STANDBY, RXLOCK, RXDMOD, TRANSMIT and RXLOCKP. These are summarized in Table I. The blocks referred to in Table I are shown also in Figure 4. These modes are described as follows:
IFIN
IFVCC1
IFVCC2
RSSI
RX
DOUT
SLEEP: STANDBY: RXLOCK:
The entire device is shut down. All functions except the regulator are shut down. The device locks to a local reference clock using the lock PLL. The lock charge pump and dividers are powered up. The VCO is also powered up. In this mode the lock charge pump and loop dividers are shut down. The receive mixer, IF strip, reference and demodulator are powered up.
IFGND
PLL DMOD REG REF
REF
DFLIP
PLLOUT VBAT VREG REG PLLVCC PLLGND
RXDMOD:
SLREF
PLL BIAS
CP
REXT CFILT COFF
TRANSMIT: This mode enables the VCO and transmit op amp. The reference and regulator are also enabled. RXLOCKP: This mode may be used in a "prior to" timeslot, i.e., the slot before the actual active receive timeslot. In this mode, after lock has been achieved in the RXLOCK mode, the receive mixer, VCO and IF strip may then be independently powered up from the demodulator loop. This can result is power savings, since the demodulator may be powered down during the IF VCO lock acquisition time.
VCO VCOGND
PLL LOCK
/3,/5 CP PD /2 REFIN REFSEL
CTL3 CTL2 CTL1 TXOUT TXOUTB
VCO
FMMOD2 FMMOD1
MODOUT
Figure 2. Power Management Scheme
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-5-
AD6402
220 A/RAD LIMITER 500 VCO 34pF 1.4k CFILT C R REFIN /2 PD 160 A/RAD CPUMP COFF COFFSET CFILT C R
PLLOUT COFF COFFSET
/3,/5
CPUMP 14 A/RAD
VCO 34pF
Figure 3a. Demodulator Block Diagram (Lock Mode)
Demodulator Operation
Figure 3b. Demodulator Block Diagram (Dmod Mode)
The PLL itself uses two loops: one for rapid frequency acquisition and a second for demodulation. The first, or frequencyacquisition loop, locks the VCO to a noninteger multiple of the system clock, either 3/2 or 5/2 (using one fixed /2 and one programmable /3 or /5 divider). This allows not only a choice of IF and system clocks but also prevents blocking of the receiver by keeping integer multiples of the system clock out of the IF passband. Once locked, this loop voltage is stored on an external capacitor and this sets the free-running frequency of the VCO during demodulation. The first loop is opened and, using the second loop and phase detector, the PLL compares the free-running frequency of its VCO to the frequency of the incoming IF. The VCO is then fast frequency locked, and slow phase locked to the incoming IF. Preconditioning of the PLL to the local reference clock facilitates the fast frequency lock to the received IF. The PLL now generates a baseband voltage proportional to the frequency deviation of the received signal. The demodulator uses a third-order PLL to track the incoming modulation signal. A simplified diagram of the demodulator is shown in Figures 3a and 3b. The loop bandwidth and damping factor can be adjusted by changing the values of C and R as indicated. An internal pole is present on the demodulator loop at approximately 9 MHz. For a loop n of 800 kHz, values of 910 pF and 330 respectively are optimum. The loop bandwidth will approximately scale inversely as the square root of the value of C. To preserve a satisfactory damping factor, R should be adjusted linearly with the loop bandwidth. At low loop bandwidths however the value of C offset must also be increased to enable the loop to lock to the reference frequency during prior to receive time slots.
APPLICATIONS
timeslot, thereby enabling a very accurate dc offset compensation of system frequency errors. The on-chip IF filter has been designed to provide some rejection of adjacent channel signals for channel bandwidths in the 1 MHz-2 MHz range. This filter has the benefit of reducing the contribution of broadband noise through the IF strip, hence improving the overall sensitivity of the receiver for a given demodulator output signal to noise ratio. It is also possible to use the AD6402 in applications where nonconstant envelope modulation schemes are used, such as QPSK. In these applications the amplitude information will be lost through the limiting action of the IF strip, but in certain applications, sufficient eye-opening will be observed in the demodulated signal to allow the use of hard decision bit-slicers as in the FM or FSK case. The actual performance of the subsystem in the presence of a QPSK signal will depend on factors such as bit rate, modulation index and BT employed. Figure 4 shows the RSSI response to a DECT signal at the IF port. It can be seen from the plot that the AD6402 can detect signals below -85 dBm and continues to detect linearly up to and above -5 dBm.
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -95
The AD6402 is optimized for use in applications where a data rate of the order of 1 megabit per second is required and the modulation scheme employed is constant envelope, i.e., FM or FSK. Because the demodulator uses a track and hold technique that locks to an externally supplied reference clock, the device is optimized for use in TDMA systems. If used in continuous demodulation applications, the dc offset hold voltage on the demodulator differential amplifier will ultimately leak away, resulting in the average dc value of the demodulator output eventually limiting against the supply rail. In a TDMA system, the voltage on the capacitor is refreshed just before the active
RSSI - V
-91
-87
-75 -55 -35 -15 INPUT POWER - dBm
-3
1
Figure 4. RSSI Response
Figure 5 shows an implementation for a DECT IF subsystem. DECT is a 1.152 megabit/second radio, employing Gaussian FSK modulation at a BT = 0.5 and uses a channel spacing of 1.728 MHz. It is a TDMA/TDD system. The IF frequency used in this application is 110.592 MHz. The AD6402's flexible power management scheme enables the part to operate at low
-6-
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AD6402
VRF C44 100nF IFVCC1 IFVCC2 C71 1nF RSSI DOUT R30 2k C58 R35 47pF 4.7k R8 4.7k C4 3.3nF RSSI RXBB C12 33pF R10 2k VRF R17 10k
IFIN C69 1nF L5 150nH
AD6402
1 2 3 4 5 B4535 10 9 8 7 6 L7 100nH L6 150nH 12pF IFGND VBAT C44 1nF VIF VREG C43 100nF SLREF VCO R26 1.2k C42 47pF D3 C41 8pF D2 L11 39nH IFC2 IFC1 C50 4.7nF SMV 1204-37 SMV 1204-36 IFC0 C28 1nF TXIF+ R21 240 TXIF- C29 1nF C30 150pF R16 330 VCOGND CTL3 CTL2 CTL1 /3,/5 CP PD CP REG C10 1nF IFIN
DFILP PLLOUT PLLVCC PLLGND REXT CP CFILT COFF
R9 1k C14 68pF
VCC
C11 100pF
VREF
REF
R22 C45 131nF 330 C31 RCLK C13 1nF R28 330 C52 100pF C51 180pF R70 R32 330 TXBB
C32 REFIN 100nF REFSEL FMMOD2
VTUNE C25 1nF
TXOUT TXOUTB MODOUT
FMMOD1
Figure 5. Application Circuit for DECT GFSK Transceiver
supply current levels when not allocated to an active transmit or receive timeslot in a TDMA system.. The respective transmit and receive blocks can be turned on only as needed thereby reducing power consumption and extending battery life of handheld terminals. The component selection in Figure 5 is explained as follows: The IF input is driven from the output of a SAW filter via an impedance matching circuit as shown. This matching minimizes the insertion loss of the filter and follows the filter manufacturers recommendations. The tank circuit shown uses two varactor diodes. One diode (D3) is biased by the output of the IF PLL loop filter and ensures that the IF VCO frequency is correctly centered. The second diode is provided to enable a modulation signal, which is generated at the output of the on-chip op amp (MODOUT), to be coupled into the VCO tank and thereby implement a modulation of the VCO frequency. In the case of DECT, the IF VCO control loop is opened while the VCO is being modulated by the transmit bit stream. The loop is opened by tri-stating the output of the IF VCO PLL charge pump. The exact component values used around the modulation amplifier will be determined by the amount of attenuation required for suppression of baseband transmit spurii and images. These artifacts are usually present if the baseband FSK signal is generated by a ROMDAC. In most instances a second or third order Bessel or Butterworth filter will be required. A capacitor to ground is required to be connected to COFF. This capacitor stores the demodulator charge-pump voltage required to lock the demodulator VCO to the reference frequency. The dynamic response of the demodulator loop is controlled by selection of the values for C45 and R22 which are connected in series to CFILT. These components determine the REV. 0 -7-
transfer characteristic of the loop filter and hence the lock time, settling time and bandwidth of the loop. REXT should use the recommended value as shown. Finally, the demodulator is followed by a voltage follower, which is configured as a data filter. This data filter is used to bandlimit the FM noise generated in the demodulator. It also attenuates undesired adjacent channel interferers. The component values chosen will be a trade-off between the amount of band limiting required and attenuation of the in-band desired signal.
DECT Application Circuit Notes (Figure 5)
1. Signal Description VRF: Regulated Supply Voltage; Nominal Value 2.85 V. VCC: Unregulated battery voltage; 3.1 V-4.5 V VTUNE: Synthesizer Control Voltage; Range dependent on loop filter and synth charge pump compliance. TXBB: Baseband transmit modulation voltage; typically SLREF 0.7 V RCLK: Reference clock for PLL demodulator; 13.824 MHz (2nd IF frequency = (N/M) x Frclk where N = 3 or 5, and M = 2. Maximum 2nd IF = c.26 MHz) 2. Typical IF input sensitivity referred to the input of SAW filter for the above application will be -72 dBm. 3. TxBB filter is user configurable. In the above application, the filter is implemented to remove images generated by ROM DAC baseband signal generators. Other implementations are possible including passive pulse shaping circuits which eliminate the need for such filtering.
AD6402
EVALUATION BOARD
An evaluation board is available for the AD6402. This board facilitates test and measurement of the subsystem. Parameters such as sensitivity, ACI, CCI, demodulator gain, demodulator offset, etc., can be quickly evaluated using this board. Contact
J1
PLLOUT DOUT SLREF PLLVCC GND IFVCC2 RSSI GND IFVCC1 REFSEL 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 NC MODIN MODOUT CTL1 CTL2 CTL3 VBATX VBAT
your local ADI sales office or ADI representative for further details on pricing and availability of the evaluation boards. Header connections details are shown in Figure 6 and available signals are shown in Figure 7. A schematic for the evaluation board is shown in Figure 8.
33pF MODOUT 33nH 3pF TP2 0.1 F 330 TP 8k 14 REXT 13 COFF 12 CFILT 1000pF TP 11 CTL1 10 CTL2 1nF 9 CTL3 8 VBAT 7 VREG 6 VCO 5 VCOGND 4 FMMOD1 3 FMMOD2 2 MODOUT 1 TXOUTB 100nF TP9 TP10 56pF MODIN TP11
TXOUTB
GND VREG
NC = NO CONNECT PLLOUT SLREF REFIN DFILP
AD6402
PLLGND PLLVCC IFVCC2 DOUT RSSI
REFSEL
IFVCC1
J1
20
SYNTH IN
REFIN
15
16
17
18
19
20
21
22
23
24
25
IFIN
Figure 6. Evaluation Board Header
IFGND
26
27
28 56pF
100pF 91pF
0.01 F
0.01 F
TP5 100
0.01 F
TXOUT
TP7 TP8
TXOUTB
1
TXOUT
2.2nF
TP6 100pF TO REFSEL PIN 2 DC CONNECTOR
AD6402
TXOUT
1.3k PLLOUT 2.2k 47pF
RSSI IFIN
IF INPUT
DOUT REFIN IFIN
NOTE: SYNTH IN, TXOUTB, TXOUT, IFIN AND REFIN CONNECTED VIA SMA CONNECTORS
Figure 8. Evaluation Board Schematic
Figure 7. Evaluation Board Connectors
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Small Shrink Outline Package (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
8 0
0.03 (0.762) 0.022 (0.558)
-8-
REV. 0
PRINTED IN U.S.A.
0.311 (7.9) 0.301 (7.64)
0.212 (5.38) 0.205 (5.21)
C3155-12-7/97

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